Senior design for test engineer
• Test plan definition for Complex SOC modem.
• Manufacturing test mode verification using vhdl test bench environment.
• Scan chain insertion using DFTMAX .
• Scan test mode verification using Tetramax tool of Synopsys.
• Scan pattern simulation using stildpv.
• Architecture & Design compensation cell Built In Self-Test engine in 65nm with vhdl.
• Functional verification of complex blocs: Digrf, DLL, PLL, DDR interface, JTAG.
• Memory bist test.
• Old life test patterns development.
Description
• Test plan definition for Complex SOC modem.
• Manufacturing test mode verification using vhdl test bench environment.
• Scan chain insertion using DFTMAX .
• Scan test mode verification using Tetramax tool of Synopsys.
• Scan pattern simulation using stildpv.
• Architecture & Design compensation cell Built In Self-Test engine in 65nm with vhdl.
• Functional verification of complex blocs: Digrf, DLL, PLL, DDR interface, JTAG.
• Memory bist test.
• Old life test patterns development.