A total of 15+ years of extensive experience in Full-custom Analog Layout for RFIC, PMIC, Mixed Signal, pure CMOS and Bi-CMOS design with 2+ years of experience as a Back-End/Physical Design Engineer. Have a portfolio of diversified and successful projects involved in a complex engineering design for 600nm down to 14nm FinFet technology process. Proactive, team player, multi-task with excellent problem solving skills that handle high pressure environments and meeting deadlines.